1. Field of the Invention
The present invention generally relates to a metal-oxide-semiconductor transistor and a method of forming gate layout, and more particularly, to a method of forming gate layout to reduce gate dishing defect and a related structure of metal-oxide-semiconductor transistor.
2. Description of the Prior Art
With advances in technology, the related industry and technology of semiconductor integrated circuit (IC) has been grown rapidly. High voltage metal-oxide-semiconductor (HV MOS) transistor devices have been broadly utilized in CPU power supply systems, power management systems, AC/DC converters, LCD/plasma TV drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, PC peripheral devices, small DC motor controllers, and other consumer electronic devices due to being capable of enduring the high voltage provided by the electrical power system and having switching characterize together.
In another aspect, as the size of device shrinks continuously, metal gate has gradually replaced the conventional polycrystalline silicon material as being the control electrode configured with high dielectric constant dielectric layer. However, the issues of process integration occur when the metal gates are applied to some specific devices, such as memory devices and high voltage devices.